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1. general description the pca9625 is an i 2 c-bus controlled 16-bit led driver optimized for voltage switch dimming and blinking 100 ma red/green/blue/amber (rgba) leds. each led output has its own 8-bit resolution (256 steps) ?xed frequency individual pwm controller that operates at 97 khz with a duty cycle that is adjustable from 0 % to 99.6 % to allow the led to be set to a speci?c brightness value. an additional 8-bit resolution (256 steps) group pwm controller has both a ?xed frequency of 190 hz and an adjustable frequency between 24 hz to once every 10.73 seconds with a duty cycle that is adjustable from 0 % to 99.6 % that is used to either dim or blink all leds with the same value. each led output can be off, on (no pwm control), set at its individual pwm controller value or at both individual and group pwm controller values. the pca9625 operates with a supply voltage range of 2.3 v to 5.5 v and the 100 ma open-drain outputs allow voltages up to 24 v. the pca9625 is one of the ?rst led controller devices in a new fast-mode plus (fm+) family. fm+ devices offer higher frequency (up to 1 mhz) and more densely populated bus operation (up to 4000 pf). the active low output enable input pin ( oe) blinks all the led outputs and can be used to externally pwm the outputs, which is useful when multiple devices need to be dimmed or blinked together without using software control. software programmable led group and three sub call i 2 c-bus addresses allow all or de?ned groups of pca9625 devices to respond to a common i 2 c-bus address, allowing for example, all red leds to be turned on or off at the same time or marquee chasing effect, thus minimizing i 2 c-bus commands. seven hardware address pins allow up to 126 devices on the same bus. the software reset (swrst) call allows the master to perform a reset of the pca9625 through the i 2 c-bus, identical to the power-on reset (por) that initializes the registers to their default state causing the outputs to be set high (led off). this allows an easy and quick way to recon?gure all device registers to the same condition. the pca9625 and pca9635 software is identical and if the pca9625 on-chip 100 ma nand fets do not provide enough current or voltage to drive the leds, then the pca9635 with larger current or higher voltage external drivers can be used. pca9625 16-bit fm+ i 2 c-bus 100 ma 24 v led driver rev. 02 15 january 2008 product data sheet
pca9625_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 january 2008 2 of 33 nxp semiconductors pca9625 16-bit fm+ i 2 c-bus 100 ma 24 v led driver 2. features n 16 led drivers. each output programmable at: u off u on u programmable led brightness u programmable group dimming/blinking mixed with individual led brightness n 1 mhz fast-mode plus compatible i 2 c-bus interface with 30 ma high drive capability on sda output for driving high capacitive buses n 256-step (8-bit) linear programmable brightness per led output varying from fully off (default) to maximum brightness using a 97 khz pwm signal n 256-step group brightness control allows general dimming (using a 190 hz pwm signal) from fully off to maximum brightness (default) n 256-step group blinking with frequency programmable from 24 hz to 10.73 s and duty cycle from 0 % to 99.6 % n sixteen open-drain outputs can sink between 0 ma to 100 ma and are tolerant to a maximum off state voltage of 24 v. no input function. n output state change programmable on the acknowledge or the stop command to update outputs byte-by-byte or all at the same time (default to change on stop). n active low output enable ( oe) input pin allows for hardware blinking and dimming of the leds n 7 hardware address pins allow 126 pca9625 devices to be connected to the same i 2 c-bus and to be individually programmed n 4 software programmable i 2 c-bus addresses (one led group call address and three led sub call addresses) allow groups of devices to be addressed at the same time in any combination (for example, one register used for all call so that all the pca9625s on the i 2 c-bus can be addressed at the same time and the second register used for three different addresses so that 1 3 of all devices on the bus can be addressed at the same time in a group). software enable and disable for i 2 c-bus address. n software reset feature (swrst call) allows the device to be reset through the i 2 c-bus n 25 mhz internal oscillator requires no external components n internal power-on reset n noise ?lter on sda/scl inputs n no glitch on power-up n supports hot insertion n low standby current n operating power supply voltage (v dd ) range of 2.3 v to 5.5 v; also requires v dd(drv)fet supply voltage range of 10 v to 24 v n 5.5 v tolerant inputs on non-led pins n - 40 c to +85 c operation n esd protection exceeds 2000 v hbm per jesd22-a114, 200 v mm per jesd22-a115 and 1000 v cdm per jesd22-c101 n latch-up testing is done to jedec standard jesd78 which exceeds 100 ma n package offered: so32
pca9625_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 january 2008 3 of 33 nxp semiconductors pca9625 16-bit fm+ i 2 c-bus 100 ma 24 v led driver 3. applications n rgb or rgba led drivers n led status information n led displays n lcd backlights n keypad backlights for cellular phones or handheld devices 4. ordering information table 1. ordering information type number topside mark package name description version pca9625d pca9625d so32 plastic small outline package; 32 leads; body width 7.5 mm sot287-1
xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x pca9625_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 january 2008 4 of 33 nxp semiconductors pca9625 16-bit fm+ i 2 c-bus 100 ma 24 v led driver 5. block diagram remark: only one led output shown for clarity. fig 1. block diagram of pca9625 a0 a1 a2 a3 a4 a5 a6 002aac786 i 2 c-bus control input filter pca9625 power-on reset scl sda v dd v ss led s tat e select register pwm register x brightness control grpfreq register grppwm register mux/ control oe '0' C permanently off '1' C permanently on ledn 190 hz 24.3 khz 97 khz 25 mhz oscillator voltage regulator v dd(drv)fet fet driver v ss(drv)fet
pca9625_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 january 2008 5 of 33 nxp semiconductors pca9625 16-bit fm+ i 2 c-bus 100 ma 24 v led driver 6. pinning information 6.1 pinning 6.2 pin description fig 2. pin con?guration for so32 pca9625d led13 led12 led14 v ss(drv)fet led15 led11 oe led10 a5 led9 a6 led8 scl v dd(drv)fet sda v ss v dd v dd(drv)fet a0 led7 a1 led6 a2 led5 a3 led4 a4 v ss(drv)fet led0 led3 led1 led2 002aac787 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18 17 20 19 22 21 24 23 26 25 32 31 30 29 28 27 table 2. pin description for so32 symbol pin type description led13 1 o led driver 13 led14 2 o led driver 14 led15 3 o led driver 15 oe 4 i active low output enable a5 5 i address input 5 a6 6 i address input 6 scl 7 i serial clock line sda 8 i/o serial data line v dd 9 power supply supply voltage a0 10 i address input 0 a1 11 i address input 1 a2 12 i address input 2 a3 13 i address input 3 a4 14 i address input 4 led0 15 o led driver 0 led1 16 o led driver 1 led2 17 o led driver 2 led3 18 o led driver 3
pca9625_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 january 2008 6 of 33 nxp semiconductors pca9625 16-bit fm+ i 2 c-bus 100 ma 24 v led driver 7. functional description refer to figure 1 bloc k diag r am of pca9625 . 7.1 device addresses following a start condition, the bus master must output the address of the slave it is accessing. there are a maximum of 128 possible programmable addresses using the 7 hardware address pins. two of these addresses, software reset and led all call, cannot be used because their default power-up state is on, leaving a maximum of 126 addresses. using other reserved addresses, as well as any other sub call address, will reduce the total number of possible addresses even further. 7.1.1 regular i 2 c-bus slave address the i 2 c-bus slave address of the pca9625 is shown in figure 3 . to conserve power, no internal pull-up resistors are incorporated on the hardware selectable address pins and they must be pulled high or low. remark: reserved i 2 c-bus addresses must be used with caution since they can interfere with: ? reserved for future use i 2 c-bus addresses (0000 011, 1111 1xx) ? slave devices that use the 10-bit addressing scheme (1111 0xx) ? slave devices that are designed to respond to the general call address (0000 000) ? high-speed mode (hs-mode) master code (0000 1xx) v ss(drv)fet 19 power supply fet driver supply ground led4 20 o led driver 4 led5 21 o led driver 5 led6 22 o led driver 6 led7 23 o led driver 7 v dd(drv)fet 24 power supply supply voltage for fet driver v ss 25 power supply supply ground v dd(drv)fet 26 power supply supply voltage for fet driver led8 27 o led driver 8 led9 28 o led driver 9 led10 29 o led driver 10 led11 30 o led driver 11 v ss(drv)fet 31 power supply fet driver supply ground led12 32 o led driver 12 table 2. pin description for so32 symbol pin type description
pca9625_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 january 2008 7 of 33 nxp semiconductors pca9625 16-bit fm+ i 2 c-bus 100 ma 24 v led driver the last bit of the address byte de?nes the operation to be performed. when set to logic 1 a read is selected, while a logic 0 selects a write operation. 7.1.2 led all call i 2 c-bus address ? default power-up value (allcalladr register): e0h or 1110 000 ? programmable through i 2 c-bus (volatile programming) ? at power-up, led all call i 2 c-bus address is enabled. pca9625 sends an ack when e0h (r/ w = 0) or e1h (r/ w = 1) is sent by the master. see section 7.3.8 allcalladr, led all call i 2 c-b us address for more detail. remark: the default led all call i 2 c-bus address (e0h or 1110 000) must not be used as a regular i 2 c-bus slave address since this address is enabled at power-up. all the pca9625s on the i 2 c-bus will acknowledge the address if sent by the i 2 c-bus master. 7.1.3 led sub call i 2 c-bus addresses ? 3 different i 2 c-bus addresses can be used ? default power-up values: C subadr1 register: e2h or 1110 001 C subadr2 register: e4h or 1110 010 C subadr3 register: e8h or 1110 100 ? programmable through i 2 c-bus (volatile programming) ? at power-up, sub call i 2 c-bus addresses are disabled. pca9625 does not send an ack when e2h (r/ w = 0) or e3h (r/ w = 1), e4h (r/ w = 0) or e5h (r/ w = 1), or e8h (r/ w = 0) or e9h (r/ w = 1) is sent by the master. see section 7.3.7 subadr1 to subadr3, i 2 c-b us subaddress 1 to 3 for more detail. remark: the default led sub call i 2 c-bus addresses may be used as regular i 2 c-bus slave addresses as long as they are disabled. 7.1.4 software reset i 2 c-bus address the address shown in figure 4 is used when a reset of the pca9625 needs to be performed by the master. the software reset address (swrst call) must be used with r/ w = logic 0. if r/ w = logic 1, the pca9625 does not acknowledge the swrst. see section 7.6 softw are reset for more detail. fig 3. slave address r/w 002aab319 a6 a5 a4 a3 a2 a1 a0 hardware selectable slave address
pca9625_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 january 2008 8 of 33 nxp semiconductors pca9625 16-bit fm+ i 2 c-bus 100 ma 24 v led driver remark: the software reset i 2 c-bus address is a reserved address and cannot be used as a regular i 2 c-bus slave address or as an led all call or led sub call address. 7.2 control register following the successful acknowledgement of the slave address, led all call address or led sub call address, the bus master will send a byte to the pca9625, which will be stored in the control register. the lowest 5 bits are used as a pointer to determine which register will be accessed (d[4:0]). the highest 3 bits are used as auto-increment ?ag and auto-increment options (ai[2:0]). when the auto-increment ?ag is set (ai2 = logic 1), the ?ve low order bits of the control register are automatically incremented after a read or write. this allows the user to program the registers sequentially. four different types of auto-increment are possible, depending on ai1 and ai0 values. remark: other combinations not shown in t ab le 3 (ai[2:0] = 001, 010, and 011) are reserved and must not be used for proper device operation. fig 4. software reset address 0 002aab416 0 0 0 0 0 1 1 r/w reset state = 80h remark: the control register does not apply to the software reset i 2 c-bus address. fig 5. control register table 3. auto-increment options ai2 ai1 ai0 function 0 0 0 no auto-increment 1 0 0 auto-increment for all registers. d[4:0] roll over to 0 0000 after the last register (1 1011) is accessed. 1 0 1 auto-increment for individual brightness registers only. d[4:0] roll over to 0 0010 after the last register (1 0001) is accessed. 1 1 0 auto-increment for global control registers only. d[4:0] roll over to 1 0010 after the last register (1 0011) is accessed. 1 1 1 auto-increment for individual and global control registers only. d[4:0] roll over to 0 0010 after the last register (1 0011) is accessed. 002aac147 ai2 ai1 ai0 d4 d3 d2 d1 d0 auto-increment flag register address auto-increment options
pca9625_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 january 2008 9 of 33 nxp semiconductors pca9625 16-bit fm+ i 2 c-bus 100 ma 24 v led driver ai[2:0] = 000 is used when the same register must be accessed several times during a single i 2 c-bus communication, for example, changes the brightness of a single led. data is overwritten each time the register is accessed during a write operation. ai[2:0] = 100 is used when all the registers must be sequentially accessed, for example, power-up programming. ai[2:0] = 101 is used when the 16 led drivers must be individually programmed with different values during the same i 2 c-bus communication, for example, changing color setting to another color setting. ai[2:0] = 110 is used when the led drivers must be globally programmed with different settings during the same i 2 c-bus communication, for example, global brightness or blinking change. ai[2:0] = 111 is used when individual and global changes must be performed during the same i 2 c-bus communication, for example, changing a color and global brightness at the same time. only the 5 least signi?cant bits d[4:0] are affected by the ai[2:0] bits. when the control register is written, the register entry point determined by d[4:0] is the ?rst register that will be addressed (read or write operation), and can be anywhere between 0 0000 and 1 1011 (as de?ned in t ab le 4 ). when ai[2] = 1, the auto-increment ?ag is set and the rollover value at which the register increment stops and goes to the next one is determined by ai[2:0]. see t ab le 3 for rollover values. for example, if the control register = 1111 0100 (f4h), then the register addressing sequence will be (in hex): 14 ? ? 1b ? 00 ? ? 13 ? 02 ? ? 13 ? 02 ? ? 13 ? 02 ? as long as the master keeps sending or reading data. 7.3 register de?nitions table 4. register summary [1] [2] register number (hex) d4 d3 d2 d1 d0 name type function 00 00000 mode1 read/write mode register 1 01 00001 mode2 read/write mode register 2 02 00010 pwm0 read/write brightness control led0 03 00011 pwm1 read/write brightness control led1 04 00100 pwm2 read/write brightness control led2 05 00101 pwm3 read/write brightness control led3 06 00110 pwm4 read/write brightness control led4 07 00111 pwm5 read/write brightness control led5 08 01000 pwm6 read/write brightness control led6 09 01001 pwm7 read/write brightness control led7 0a 01010 pwm8 read/write brightness control led8 0b 01011 pwm9 read/write brightness control led9 0c 01100 pwm10 read/write brightness control led10 0d 01101 pwm11 read/write brightness control led11 0e 01110 pwm12 read/write brightness control led12
pca9625_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 january 2008 10 of 33 nxp semiconductors pca9625 16-bit fm+ i 2 c-bus 100 ma 24 v led driver [1] only d[4:0] = 0 0000 to 1 1011 are allowed and will be acknowledged. d[4:0] = 1 1100 to 1 1111 are reserved and will not be acknowledged. [2] when writing to the control register, bit 4 must be programmed with logic 0 for proper device operation. 7.3.1 mode register 1, mode1 [1] it takes 500 m s max. for the oscillator to be up and running once sleep bit has been set to logic 1. timings on ledn outputs are not guaranteed if pwmx, grppwm or grpfreq registers are accessed within the 500 m s window. [2] no blinking or dimming is possible when the oscillator is off. 0f 01111 pwm13 read/write brightness control led13 10 10000 pwm14 read/write brightness control led14 11 10001 pwm15 read/write brightness control led15 12 10010 grppwm read/write group duty cycle control 13 10011 grpfreq read/write group frequency 14 10100 ledout0 read/write led output state 0 15 10101 ledout1 read/write led output state 1 16 10110 ledout2 read/write led output state 2 17 10111 ledout3 read/write led output state 3 18 11000 subadr1 read/write i 2 c-bus subaddress 1 19 11001 subadr2 read/write i 2 c-bus subaddress 2 1a 11010 subadr3 read/write i 2 c-bus subaddress 3 1b 11011 allcalladr read/write led all call i 2 c-bus address table 4. register summary [1] [2] continued register number (hex) d4 d3 d2 d1 d0 name type function table 5. mode1 - mode register 1 (address 00h) bit description legend: * default value. bit symbol access value description 7 ai2 read only 0 register auto-increment disabled. 1* register auto-increment enabled. 6 ai1 read only 0* auto-increment bi t1=0. 1 auto-increment bi t1=1. 5 ai0 read only 0* auto-increment bi t0=0. 1 auto-increment bi t0=1. 4 sleep r/w 0 normal mode [1] . 1* low power mode. oscillator off [2] . 3 sub1 r/w 0* pca9625 does not respond to i 2 c-bus subaddress 1. 1 pca9625 responds to i 2 c-bus subaddress 1. 2 sub2 r/w 0* pca9625 does not respond to i 2 c-bus subaddress 2. 1 pca9625 responds to i 2 c-bus subaddress 2. 1 sub3 r/w 0* pca9625 does not respond to i 2 c-bus subaddress 3. 1 pca9625 responds to i 2 c-bus subaddress 3. 0 allcall r/w 0 pca9625 does not respond to led all call i 2 c-bus address. 1* pca9625 responds to led all call i 2 c-bus address.
pca9625_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 january 2008 11 of 33 nxp semiconductors pca9625 16-bit fm+ i 2 c-bus 100 ma 24 v led driver 7.3.2 mode register 2, mode2 [1] change of the outputs at the stop command allows synchronizing outputs of more than one pca9625. applicable to registers from 02h (pwm0) to 08h (ledout) only. 7.3.3 pwm0 to pwm15, individual brightness control table 6. mode2 - mode register 2 (address 01h) bit description legend: * default value. bit symbol access value description 7 - read only 0* reserved 6 - read only 0* reserved 5 dmblnk r/w 0* group control = dimming. 1 group control = blinking. 4 invrt r/w 0* reserved; write must always be a logic 0 3 och r/w 0* outputs change on stop command [1] 1 outputs change on ack 2 - r/w 1* reserved; write must always be a logic 1 1 - r/w 0* reserved; write must always be a logic 0 0 - r/w 1* reserved; write must always be a logic 1 table 7. pwm0 to pwm15 - pwm registers 0 to 15 (address 02h to 11h) bit description legend: * default value. address register bit symbol access value description 02h pwm0 7:0 idc0[7:0] r/w 0000 0000* pwm0 individual duty cycle 03h pwm1 7:0 idc1[7:0] r/w 0000 0000* pwm1 individual duty cycle 04h pwm2 7:0 idc2[7:0] r/w 0000 0000* pwm2 individual duty cycle 05h pwm3 7:0 idc3[7:0] r/w 0000 0000* pwm3 individual duty cycle 06h pwm4 7:0 idc4[7:0] r/w 0000 0000* pwm4 individual duty cycle 07h pwm5 7:0 idc5[7:0] r/w 0000 0000* pwm5 individual duty cycle 08h pwm6 7:0 idc6[7:0] r/w 0000 0000* pwm6 individual duty cycle 09h pwm7 7:0 idc7[7:0] r/w 0000 0000* pwm7 individual duty cycle 0ah pwm8 7:0 idc8[7:0] r/w 0000 0000* pwm8 individual duty cycle 0bh pwm9 7:0 idc9[7:0] r/w 0000 0000* pwm9 individual duty cycle 0ch pwm10 7:0 idc10[7:0] r/w 0000 0000* pwm10 individual duty cycle 0dh pwm11 7:0 idc11[7:0] r/w 0000 0000* pwm11 individual duty cycle 0eh pwm12 7:0 idc12[7:0] r/w 0000 0000* pwm12 individual duty cycle 0fh pwm13 7:0 idc13[7:0] r/w 0000 0000* pwm13 individual duty cycle 10h pwm14 7:0 idc14[7:0] r/w 0000 0000* pwm14 individual duty cycle 11h pwm15 7:0 idc15[7:0] r/w 0000 0000* pwm15 individual duty cycle
pca9625_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 january 2008 12 of 33 nxp semiconductors pca9625 16-bit fm+ i 2 c-bus 100 ma 24 v led driver a 97 khz ?xed frequency signal is used for each output. duty cycle is controlled through 256 linear steps from 00h (0 % duty cycle = led output off) to ffh (99.6 % duty cycle = led output at maximum brightness). applicable to led outputs programmed with ldrx = 10 or 11 (ledout0 to ledout3 registers). (1) 7.3.4 grppwm, group duty cycle control when dmblnk bit (mode2 register) is programmed with logic 0, a 190 hz ?xed frequency signal is superimposed with the 97 khz individual brightness control signal. grppwm is then used as a global brightness control allowing the led outputs to be dimmed with the same value. the value in grpfreq is then a dont care. general brightness for the 16 outputs is controlled through 256 linear steps from 00h (0 % duty cycle = led output off) to ffh (99.6 % duty cycle = maximum brightness). applicable to led outputs programmed with ldrx = 11 (ledout0 to ledout3 registers). when dmblnk bit is programmed with logic 1, grppwm and grpfreq registers de?ne a global blinking pattern, where grpfreq contains the blinking period (from 24 hz to 10.73 s) and grppwm the duty cycle (on/off ratio in %). (2) 7.3.5 grpfreq, group frequency grpfreq is used to program the global blinking period when dmblnk bit (mode2 register) is equal to 1. value in this register is a dont care when dmblnk = 0. applicable to led outputs programmed with ldrx = 11 (ledout0 to ledout3 registers). blinking period is controlled through 256 linear steps from 00h (41 ms, frequency 24 hz) to ffh (10.73 s). (3) duty cycle idcx 7 : 0 [] 256 --------------------------- = table 8. grppwm - group brightness control register (address 12h) bit description legend: * default value address register bit symbol access value description 12h grppwm 7:0 gdc[7:0] r/w 1111 1111 grppwm register duty cycle gdc 7 : 0 [] 256 -------------------------- - = table 9. grpfreq - group frequency register (address 13h) bit description legend: * default value. address register bit symbol access value description 13h grpfreq 7:0 gfrq[7:0] r/w 0000 0000* grpfreq register global blinking period gfrq 7 : 0 [] 1 + 24 --------------------------------------- - s () =
pca9625_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 january 2008 13 of 33 nxp semiconductors pca9625 16-bit fm+ i 2 c-bus 100 ma 24 v led driver 7.3.6 ledout0 to ledout3, led driver output state ldrx = 00 led driver x is off (default power-up state). ldrx = 01 led driver x is fully on (individual brightness and group dimming/blinking not controlled). ldrx = 10 led driver x individual brightness can be controlled through its pwmx register. ldrx = 11 led driver x individual brightness and group dimming/blinking can be controlled through its pwmx register and the grppwm registers. 7.3.7 subadr1 to subadr3, i 2 c-bus subaddress 1 to 3 subaddresses are programmable through the i 2 c-bus. default power-up values are e2h, e4h, e8h, and the device(s) will not acknowledge these addresses right after power-up (the corresponding subx bit in mode1 register is equal to 0). table 10. ledout0 to ledout3 - led driver output state register (address 14h to 17h) bit description legend: * default value. address register bit symbol access value description 14h ledout0 7:6 ldr3 r/w 00* led3 output state control 5:4 ldr2 r/w 00* led2 output state control 3:2 ldr1 r/w 00* led1 output state control 1:0 ldr0 r/w 00* led0 output state control 15h ledout1 7:6 ldr7 r/w 00* led7 output state control 5:4 ldr6 r/w 00* led6 output state control 3:2 ldr5 r/w 00* led5 output state control 1:0 ldr4 r/w 00* led4 output state control 16h ledout2 7:6 ldr11 r/w 00* led11 output state control 5:4 ldr10 r/w 00* led10 output state control 3:2 ldr9 r/w 00* led9 output state control 1:0 ldr8 r/w 00* led8 output state control 17h ledout3 7:6 ldr15 r/w 00* led15 output state control 5:4 ldr14 r/w 00* led14 output state control 3:2 ldr13 r/w 00* led13 output state control 1:0 ldr12 r/w 00* led12 output state control table 11. subadr1 to subadr3 - i 2 c-bus subaddress registers 0 to 3 (address 18h to 1ah) bit description legend: * default value. address register bit symbol access value description 18h subadr1 7:1 a1[7:1] r/w 1110 001* i 2 c-bus subaddress 1 0 a1[0] r only 0* reserved 19h subadr2 7:1 a2[7:1] r/w 1110 010* i 2 c-bus subaddress 2 0 a2[0] r only 0* reserved 1ah subadr3 7:1 a3[7:1] r/w 1110 100* i 2 c-bus subaddress 3 0 a3[0] r only 0* reserved
pca9625_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 january 2008 14 of 33 nxp semiconductors pca9625 16-bit fm+ i 2 c-bus 100 ma 24 v led driver once subaddresses have been programmed to their right values, subx bits need to be set to logic 1 in order to have the device acknowledging these addresses (mode1 register). only the 7 msbs representing the i 2 c-bus subaddress are valid. the lsb in subadrx register is a read-only bit (0). when subx is set to logic 1, the corresponding i 2 c-bus subaddress can be used during either an i 2 c-bus read or write sequence. 7.3.8 allcalladr, led all call i 2 c-bus address the led all call i 2 c-bus address allows all the pca9625s on the bus to be programmed at the same time (allcall bit in register mode1 must be equal to 1 (power-up default state)). this address is programmable through the i 2 c-bus and can be used during either an i 2 c-bus read or write sequence. the register address can also be programmed as a sub call. only the 7 msbs representing the all call i 2 c-bus address are valid. the lsb in allcalladr register is a read-only bit (0). if allcall bit = 0, the device does not acknowledge the address programmed in register allcalladr. 7.4 active low output enable input the active low output enable ( oe) pin, allows to enable or disable all the led outputs at the same time. ? when a low level is applied to oe pin, all the led outputs are enabled. ? when a high level is applied to oe pin, all the led outputs are high-impedance. the oe pin can be used as a synchronization signal to switch on/off several pca9625 devices at the same time. this requires an external clock reference that provides blinking period and the duty cycle. the oe pin can also be used as an external dimming control signal. the frequency of the external clock must be high enough not to be seen by the human eye, and the duty cycle value determines the brightness of the leds. remark: do not use oe as an external blinking control signal when internal global blinking is selected (dmblnk = 1, mode2 register) since it will result in an unde?ned blinking pattern. do not use oe as an external dimming control signal when internal global dimming is selected (dmblnk = 0, mode2 register) since it will result in an unde?ned dimming pattern. table 12. allcalladr - led all call i 2 c-bus address register (address 1bh) bit description legend: * default value. address register bit symbol access value description 1bh allcalladr 7:1 ac[7:1] r/w 1110 000* allcall i 2 c-bus address register 0 ac[0] r only 0* reserved
pca9625_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 january 2008 15 of 33 nxp semiconductors pca9625 16-bit fm+ i 2 c-bus 100 ma 24 v led driver 7.5 power-on reset when power is applied to v dd , an internal power-on reset holds the pca9625 in a reset condition until v dd has reached v por . at this point, the reset condition is released and the pca9625 registers and i 2 c-bus state machine are initialized to their default states (all zeroes) causing all the channels to be deselected. thereafter, v dd must be lowered below 0.2 v to reset the device. 7.6 software reset the software reset call (swrst call) allows all the devices in the i 2 c-bus to be reset to the power-up state value through a speci?c formatted i 2 c-bus command. to be performed correctly, it implies that the i 2 c-bus is functional and that there is no device hanging the bus. the swrst call function is de?ned as the following: 1. a start command is sent by the i 2 c-bus master. 2. the reserved swrst i 2 c-bus address 0000 011 with the r/ w bit set to 0 (write) is sent by the i 2 c-bus master. 3. the pca9625 device(s) acknowledge(s) after seeing the swrst call address 0000 0110 (06h) only. if the r/ w bit is set to 1 (read), no acknowledge is returned to the i 2 c-bus master. 4. once the swrst call address has been sent and acknowledged, the master sends 2 bytes with 2 speci?c values (swrst data byte 1 and byte 2): a. byte 1 = a5h: the pca9625 acknowledges this value only. if byte 1 is not equal to a5h, the pca9625 does not acknowledge it. b. byte 2 = 5ah: the pca9625 acknowledges this value only. if byte 2 is not equal to 5ah, then the pca9625 does not acknowledge it. if more than 2 bytes of data are sent, the pca9625 does not acknowledge any more. 5. once the right 2 bytes (swrst data byte 1 and byte 2 only) have been sent and correctly acknowledged, the master sends a stop command to end the swrst call: the pca9625 then resets to the default value (power-up value) and is ready to be addressed again within the speci?ed bus free time (t buf ). the i 2 c-bus master must interpret a non-acknowledge from the pca9625 (at any time) as a swrst call abort. the pca9625 does not initiate a reset of its registers. this happens only when the format of the swrst call sequence is not correct.
pca9625_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 january 2008 16 of 33 nxp semiconductors pca9625 16-bit fm+ i 2 c-bus 100 ma 24 v led driver 7.7 individual brightness control with group dimming/blinking a 97 khz ?xed frequency signal with programmable duty cycle (8 bits, 256 steps) is used to control individually the brightness for each led. on top of this signal, one of the following signals can be superimposed (this signal can be applied to the 4 led outputs): ? a lower 190 hz ?xed frequency signal with programmable duty cycle (8 bits, 256 steps) is used to provide a global brightness control. ? a programmable frequency signal from 24 hz to 1 10.73 hz (8 bits, 256 steps) with programmable duty cycle (8 bits, 256 steps) is used to provide a global blinking control. minimum pulse width for ledn brightness control is 40 ns. minimum pulse width for group dimming is 20.48 m s. when m = 1 (grppwm register value), the resulting ledn brightness control + group dimming signal will have 2 pulses of the led brightness control signal (pulse width = n 40 ns, with n de?ned in pwmx register). this resulting brightness + group dimming signal above shows a resulting control signal with m = 4 (8 pulses). fig 6. brightness + group dimming signals 123456789101112 507 508 509 510 511 512 1234567891011 brightness control signal (ledn) m 256 2 40 ns with m = (0 to 255) (grppwm register) n 40 ns with n = (0 to 255) (pwmx register) 256 40 ns = 10.24 m s (97.6 khz) 12345678 12345678 group dimming signal resulting brightness + group dimming signal 256 2 256 40 ns = 5.24 ms (190.7 hz) 002aab417
pca9625_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 january 2008 17 of 33 nxp semiconductors pca9625 16-bit fm+ i 2 c-bus 100 ma 24 v led driver 8. characteristics of the i 2 c-bus the i 2 c-bus is for 2-way, 2-line communication between different ics or modules. the two lines are a serial data line (sda) and a serial clock line (scl). both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. data transfer may be initiated only when the bus is not busy. 8.1 bit transfer one data bit is transferred during each clock pulse. the data on the sda line must remain stable during the high period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see figure 7 ). 8.1.1 start and stop conditions both data and clock lines remain high when the bus is not busy. a high-to-low transition of the data line while the clock is high is de?ned as the start condition (s). a low-to-high transition of the data line while the clock is high is de?ned as the stop condition (p) (see figure 8 ). 8.2 system con?guration a device generating a message is a transmitter; a device receiving is the receiver. the device that controls the message is the master and the devices which are controlled by the master are the slaves (see figure 9 ). fig 7. bit transfer mba607 data line stable; data valid change of data allowed sda scl fig 8. de?nition of start and stop conditions mba608 sda scl p stop condition sda scl s start condition
pca9625_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 january 2008 18 of 33 nxp semiconductors pca9625 16-bit fm+ i 2 c-bus 100 ma 24 v led driver 8.3 acknowledge the number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. each byte of eight bits is followed by one acknowledge bit. the acknowledge bit is a high level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse. a slave receiver which is addressed must generate an acknowledge after the reception of each byte. also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse, so that the sda line is stable low during the high period of the acknowledge related clock pulse; set-up time and hold time must be taken into account. a master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this event, the transmitter must leave the data line high to enable the master to generate a stop condition. fig 9. system con?guration 002aaa966 master transmitter/ receiver slave receiver slave transmitter/ receiver master transmitter master transmitter/ receiver sda scl i 2 c-bus multiplexer slave fig 10. acknowledgement on the i 2 c-bus 002aaa987 s start condition 9 8 2 1 clock pulse for acknowledgement not acknowledge acknowledge data output by transmitter data output by receiver scl from master
pca9625_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 january 2008 19 of 33 nxp semiconductors pca9625 16-bit fm+ i 2 c-bus 100 ma 24 v led driver 9. bus transactions (1) see t ab le 4 for register de?nition. fig 11. write to a speci?c register a5 a4 a3 a2 a1 a0 0 a s a6 slave address start condition r/w acknowledge from slave 002aac148 data for register d[4:0] (1) x x d4 d3 d2 d1 d0 x control register auto-increment flag auto-increment options a acknowledge from slave a acknowledge from slave p stop condition fig 12. write to all registers using the auto-increment feature a5 a4 a3 a2 a1 a0 0 a s a6 slave address start condition r/w acknowledge from slave 002aac149 mode1 register 0 0 0 0 0 0 0 1 control register auto-increment on auto-increment on all registers a acknowledge from slave a acknowledge from slave p stop condition (cont.) (cont.) mode1 register selection mode2 register a acknowledge from slave subadr3 register a acknowledge from slave allcalladr register a acknowledge from slave fig 13. multiple writes to individual brightness registers only using the auto-increment feature a5 a4 a3 a2 a1 a0 0 a s a6 slave address start condition r/w acknowledge from slave 002aac150 pwm0 register 0 1 0 0 0 1 0 1 control register auto-increment on increment on individual brightness registers only a acknowledge from slave a acknowledge from slave p stop condition (cont.) (cont.) pwm0 register selection pwm1 register a acknowledge from slave pwm14 register a acknowledge from slave pwm15 register a acknowledge from slave pwm0 register a acknowledge from slave pwmx register a acknowledge from slave
pca9625_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 january 2008 20 of 33 nxp semiconductors pca9625 16-bit fm+ i 2 c-bus 100 ma 24 v led driver fig 14. read all registers using the auto-increment feature a5 a4 a3 a2 a1 a0 0 a s a6 slave address start condition r/w acknowledge from slave 002aac151 0 0 0 0 0 0 0 1 control register auto-increment on auto-increment on all registers a acknowledge from slave (cont.) (cont.) mode1 register selection data from mode1 register a acknowledge from master sr restart condition a5 a4 a3 a2 a1 a0 1 a a6 slave address r/w acknowledge from slave data from mode2 register a acknowledge from master data from pwm0 a acknowledge from master data from allcalladr register a acknowledge from master data from mode1 register a acknowledge from master (cont.) (cont.) data from last read byte a not acknowledge from master p stop condition (1) in this example, several pca9625s are used and the same sequence (a) (above) is sent to each of them. (2) allcall bit in mode1 register is equal to 1 for this example. (3) och bit in mode2 register is equal to 1 for this example. fig 15. led all call i 2 c-bus address programming and led all call sequence example a5 a4 a3 a2 a1 a0 0 a s a6 slave address (1) start condition r/w acknowledge from slave 002aac152 x x 1 1 0 1 1 x control register auto-increment on a acknowledge from slave allcalladr register selection 0 1 0 1 0 1 x 1 new led all call i 2 c address (2) p stop condition a acknowledge from slave 0 1 0 1 0 1 0 a s 1 led all call i 2 c address start condition r/w acknowledge from the 4 devices x x 0 1 0 0 0 x control register a acknowledge from the 4 devices ledout register selection 1 0 1 0 1 0 1 0 ledout register (led fully on) p stop condition a acknowledge from the 4 devices the 16 leds are on at the acknowledge (3) sequence (a) sequence (b)
pca9625_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 january 2008 21 of 33 nxp semiconductors pca9625 16-bit fm+ i 2 c-bus 100 ma 24 v led driver 10. application design-in information (1) oe requires pull-up resistor if control signal from the master is open-drain. i 2 c-bus address = 0010 101x. fig 16. typical application pca9625 led0 led1 sda scl oe v dd = 2.5 v, 3.3 v or 5.0 v i 2 c-bus/smbus master sda scl 10 k w oe 10 k w led2 led3 a0 a1 a2 v dd a3 a4 a5 a6 v ss 10 v to 24 v 10 k w (1) up to 24 v led8 led9 led10 led11 v dd(drv)fet led4 led5 led6 led7 up to 24 v led light bar led12 led13 led14 led15 up to 24 v led light bar 002aac788 v ss(drv)fet up to 24 v
pca9625_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 january 2008 22 of 33 nxp semiconductors pca9625 16-bit fm+ i 2 c-bus 100 ma 24 v led driver 11. limiting values [1] the v drv(led) must always be less than or equal to v dd(drv)fet . 12. thermal characteristics table 13. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v dd supply voltage - 0.5 +6.0 v v i/o voltage on an input/output pin v ss - 0.5 5.5 v v drv(led) led driver voltage [1] v ss - 0.5 24 v v dd(drv)fet fet driver supply voltage [1] v ss - 0.5 24 v i o(ledn) output current on pin ledn - 100 ma i ss ground supply current per v ss(drv)fet pin - 800 ma p tot total power dissipation t amb =25 c - 1.8 w t amb =85 c - 0.72 w p/ch power dissipation per channel t amb =25 c - 100 mw t amb =85 c - 45 mw t stg storage temperature - 65 +150 c t amb ambient temperature operating - 40 +85 c table 14. thermal characteristics symbol parameter conditions typ unit r th(j-a) thermal resistance from junction to ambient so32 55 c/w
pca9625_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 january 2008 23 of 33 nxp semiconductors pca9625 16-bit fm+ i 2 c-bus 100 ma 24 v led driver 13. static characteristics table 15. static characteristics v dd = 2.3 v to 5.5 v; v ss =0v; t amb = - 40 cto+85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit supply v dd(drv)fet fet driver supply voltage 10 - 24 v v dd supply voltage 2.3 - 5.5 v i dd supply current on pin v dd (pin 9); operating mode; no load; f scl = 1 mhz v dd = 2.3 v - 2.5 10 ma v dd = 3.3 v - 2.5 10 ma v dd = 5.5 v - 2.5 10 ma i stb standby current on pin v dd (pin 9); no load; f scl = 0 hz; i/o = inputs; v i =v dd v dd = 2.3 v - 1.3 5 m a v dd = 3.3 v - 1.4 6 m a v dd = 5.5 v - 1.5 7 m a on pin v dd(drv)fet (pin 24 and pin 26) v dd(drv)fet = 18 v - 400 1000 m a v por power-on reset voltage no load; v i =v dd or v ss [1] - 1.70 2.0 v input scl; input/output sda v il low-level input voltage - 0.5 - +0.3v dd v v ih high-level input voltage 0.7v dd - 5.5 v i ol low-level output current v ol = 0.4 v; v dd = 2.3 v 20 - - ma v ol = 0.4 v; v dd = 5.0 v 30 - - ma i l leakage current v i =v dd or v ss - 1- +1 m a c i input capacitance v i =v ss - 6 10 pf led driver outputs v drv(led) led driver voltage [2] 0 - 24 v i ol low-level output current v ol = 0.5 v [3] 100 - - ma i ol(tot) total low-level output current v ol = 0.5 v [3] 1600 - - ma r on on-state resistance v dd(drv)fet =10v; v dd = 2.3 v -2 5 w c o output capacitance - 2.5 5 pf oe input v il low-level input voltage - 0.5 - +0.8 v v ih high-level input voltage 2 - 5.5 v i li input leakage current - 1- +1 m a c i input capacitance - 3.7 5 pf
pca9625_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 january 2008 24 of 33 nxp semiconductors pca9625 16-bit fm+ i 2 c-bus 100 ma 24 v led driver [1] v dd must be lowered to 0.2 v in order to reset part. [2] v dd(drv)fet and v drv(led) voltages are independent, but v drv(led) v dd(drv)fet at all times. [3] each bit must be limited to a maximum of 100 ma and the total package limited to 1600 ma due to internal busing limits. 14. dynamic characteristics [1] t vd;ack = time for acknowledgement signal from scl low to sda (out) low. [2] t vd;dat = minimum time for sda data out to be valid following scl low. [3] a master device must internally provide a hold time of at least 300 ns for the sda signal (refer to the v il of the scl signal) in order to bridge the unde?ned region of scls falling edge. address inputs v il low-level input voltage - 0.5 - +0.3v dd v v ih high-level input voltage 0.7v dd - 5.5 v i li input leakage current - 1- +1 m a c i input capacitance - 3.7 5 pf table 15. static characteristics continued v dd = 2.3 v to 5.5 v; v ss =0v; t amb = - 40 cto+85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit table 16. dynamic characteristics symbol parameter conditions standard-mode i 2 c-bus fast-mode i 2 c-bus fast-mode plus i 2 c-bus unit min max min max min max f scl scl clock frequency 0 100 0 400 0 1000 khz t buf bus free time between a stop and start condition 4.7 - 1.3 - 0.5 - m s t hd;sta hold time (repeated) start condition 4.0 - 0.6 - 0.26 - m s t su;sta set-up time for a repeated start condition 4.7 - 0.6 - 0.26 - m s t su;sto set-up time for stop condition 4.0 - 0.6 - 0.26 - m s t hd;dat data hold time 0 - 0 - 0 - ns t vd;ack data valid acknowledge time [1] 0.3 3.45 0.1 0.9 0.05 0.45 m s t vd;dat data valid time [2] 0.3 3.45 0.1 0.9 0.05 0.45 m s t su;dat data set-up time 250 - 100 - 50 - ns t low low period of the scl clock 4.7 - 1.3 - 0.5 - m s t high high period of the scl clock 4.0 - 0.6 - 0.26 - m s t f fall time of both sda and scl signals [3] [4] - 300 20 + 0.1c b [5] 300 - 120 ns t r rise time of both sda and scl signals - 1000 20 + 0.1c b [5] 300 - 120 ns t sp pulse width of spikes that must be suppressed by the input ?lter [6] - 50 - 50 - 50 ns
pca9625_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 january 2008 25 of 33 nxp semiconductors pca9625 16-bit fm+ i 2 c-bus 100 ma 24 v led driver [4] the maximum t f for the sda and scl bus lines is speci?ed at 300 ns. the maximum fall time (t f ) for the sda output stage is speci?ed at 250 ns. this allows series protection resistors to be connected between the sda and the scl pins and the sda/scl bus lines witho ut exceeding the maximum speci?ed t f . [5] c b = total capacitance of one bus line in pf. [6] input ?lters on the sda and scl inputs suppress noise spikes less than 50 ns. fig 17. de?nition of timing t sp t buf t hd;sta p p s t low t r t hd;dat t f t high t su;dat t su;sta sr t hd;sta t su;sto sda scl 002aaa986 rise and fall times refer to v il and v ih . fig 18. i 2 c-bus timing diagram scl sda t hd;sta t su;dat t hd;dat t f t buf t su;sta t low t high t vd;ack 002aab285 t su;sto protocol start condition (s) bit 7 msb (a7) bit 6 (a6) bit 1 (d1) bit 0 (d0) 1 / f scl t r t vd;dat acknowledge (a) stop condition (p)
pca9625_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 january 2008 26 of 33 nxp semiconductors pca9625 16-bit fm+ i 2 c-bus 100 ma 24 v led driver 15. test information r l = load resistor for ledn. r l for sda and scl > 1 k w (3 ma or less current). c l = load capacitance includes jig and probe capacitance. r t = termination resistance should be equal to the output impedance z o of the pulse generators. fig 19. test circuitry for switching times pulse generator v o c l 50 pf r l 500 w 002aab284 r t v i v dd dut v dd open gnd
pca9625_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 january 2008 27 of 33 nxp semiconductors pca9625 16-bit fm+ i 2 c-bus 100 ma 24 v led driver 16. package outline fig 20. package outline sot287-1 (so32) unit a max. a 1 a 2 a 3 b p cd (1) e (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm inches 2.65 0.1 0.25 0.01 1.4 0.055 0.3 0.1 2.45 2.25 0.49 0.36 0.27 0.18 20.7 20.3 7.6 7.4 1.27 10.65 10.00 1.2 1.0 0.95 0.55 8 0 o o 0.25 0.1 0.004 0.25 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.1 0.4 sot287-1 mo-119 (1) 0.012 0.004 0.096 0.089 0.02 0.01 0.05 0.047 0.039 0.419 0.394 0.30 0.29 0.81 0.80 0.011 0.007 0.037 0.022 0.01 0.01 0.043 0.016 w m b p d h e z e c v m a x a y 32 17 16 1 q a a 1 a 2 l p q detail x l (a ) 3 e pin 1 index 0 5 10 mm scale so32: plastic small outline package; 32 leads; body width 7.5 mm sot287-1 00-08-17 03-02-19
pca9625_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 january 2008 28 of 33 nxp semiconductors pca9625 16-bit fm+ i 2 c-bus 100 ma 24 v led driver 17. handling information inputs and outputs are protected against electrostatic discharge in normal handling. however, to be completely safe you must take normal precautions appropriate to handling integrated circuits. 18. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 surface mount re?ow soldering description . 18.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electrical circuits. the soldered joint provides both the mechanical and the electrical connection. there is no single soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for ?ne pitch smds. re?ow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 18.2 wave and re?ow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. the re?ow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature pro?le. leaded packages, packages with solder balls, and leadless packages are all re?ow solderable. key characteristics in both wave and re?ow soldering are: ? board speci?cations, including the board ?nish, solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivity level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 18.3 wave soldering key characteristics in wave soldering are:
pca9625_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 january 2008 29 of 33 nxp semiconductors pca9625 16-bit fm+ i 2 c-bus 100 ma 24 v led driver ? process issues, such as application of adhesive and ?ux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath speci?cations, including temperature and impurities 18.4 re?ow soldering key characteristics in re?ow soldering are: ? lead-free versus snpb soldering; note that a lead-free re?ow process usually leads to higher minimum peak temperatures (see figure 21 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? re?ow temperature pro?le; this pro?le includes preheat, re?ow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classi?ed in accordance with t ab le 17 and 18 moisture sensitivity precautions, as indicated on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during re?ow soldering, see figure 21 . table 17. snpb eutectic process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 3 350 < 2.5 235 220 3 2.5 220 220 table 18. lead-free process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
pca9625_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 january 2008 30 of 33 nxp semiconductors pca9625 16-bit fm+ i 2 c-bus 100 ma 24 v led driver for further information on temperature pro?les, refer to application note an10365 surface mount re?ow soldering description . 19. abbreviations msl: moisture sensitivity level fig 21. temperature pro?les for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature table 19. abbreviations acronym description cdm charged device model dut device under test esd electrostatic discharge fet field-effect transistor hbm human body model i 2 c-bus inter-integrated circuit bus led light emitting diode lsb least signi?cant bit mm machine model msb most signi?cant bit nmos negative-channel metal oxide semiconductor npn bipolar transistor with n-type emitter and collector and a p-type base pcb printed-circuit board pmos positive-channel metal oxide semiconductor pnp bipolar transistor with p-type emitter and collector and an n-type base pwm pulse width modulation rgb red/green/blue rgba red/green/blue/amber smbus system management bus
pca9625_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 january 2008 31 of 33 nxp semiconductors pca9625 16-bit fm+ i 2 c-bus 100 ma 24 v led driver 20. revision history table 20. revision history document id release date data sheet status change notice supersedes pca9625_2 20080115 product data sheet - pca9625_1 modi?cations: ? section 2 f eatures , 6 th bullet item re-written ? section 7.2 control register , 3rd paragraph following t ab le 3 changed from ai[2:0] = 101 is used when the four led drivers ... to ai[2:0] = 101 is used when the 16 led drivers ... ? t ab le 6 mode2 - mode register 2 (address 01h) bit descr iption : bit 1 and bit 0 descriptions re-written ? t ab le 13 limiting v alues : C symbol p tot : added separate speci?cations for conditions t amb =25 c and t amb =85 c C added speci?cation for p/ch, power dissipation per channel C added t ab le note [1] ? added section 12 ther mal char acter istics ? t ab le 15 static char acter istics , sub-section supply, i dd : added on pin v dd (pin 9) to conditions column ? t ab le 15 static char acter istics , sub-section supply, i stb : C added on pin v dd (pin 9) to conditions column C for condition v dd = 2.3 v, changed typ value from 2.3 m a to 1.3 m a; changed max value from 11 m a to 5 m a C for condition v dd = 3.3 v, changed typ value from 2.9 m a to 1.4 m a; changed max value from 12 m a to 6 m a C for condition v dd = 5.5 v, changed typ value from 3.8 m a to 1.5 m a; changed max value from 15.5 m a to 7 m a C added separate speci?cations for condition on pin v dd(drv)fet (pin 24 and pin 26) ? t ab le 15 static char acter istics , sub-section led driver outputs: added r on speci?cation ? t ab le 15 static char acter istics , t ab le note [2] re-written pca9625_1 20070917 objective data sheet - -
pca9625_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 january 2008 32 of 33 nxp semiconductors pca9625 16-bit fm+ i 2 c-bus 100 ma 24 v led driver 21. legal information 21.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term short data sheet is explained in section de?nitions. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple dev ices. the latest product status information is available on the internet at url http://www .nxp .com . 21.2 de?nitions draft the document is a draft version only. the content is still under internal review and subject to formal approval, which may result in modi?cations or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. short data sheet a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request via the local nxp semiconductors sales of?ce. in case of any inconsistency or con?ict with the short data sheet, the full data sheet shall prevail. 21.3 disclaimers general information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes nxp semiconductors reserves the right to make changes to information published in this document, including without limitation speci?cations and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. applications applications that are described herein for any of these products are for illustrative purposes only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. limiting values stress above one or more limiting values (as de?ned in the absolute maximum ratings system of iec 60134) may cause permanent damage to the device. limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale nxp semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www .nxp .com/pro? le/ter ms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by nxp semiconductors. in case of any inconsistency or con?ict between information in this document and such terms and conditions, the latter will prevail. no offer to sell or license nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 21.4 trademarks notice: all referenced brands, product names, service names and trademarks are the property of their respective owners. i 2 c-bus logo is a trademark of nxp b.v. 22. contact information for more information, please visit: http://www .nxp.com for sales of?ce addresses, please send an email to: salesad dresses@nxp.com document status [1] [2] product status [3] de?nition objective [short] data sheet development this document contains data from the objective speci?cation for product development. preliminary [short] data sheet quali?cation this document contains data from the preliminary speci?cation. product [short] data sheet production this document contains the product speci?cation.
nxp semiconductors pca9625 16-bit fm+ i 2 c-bus 100 ma 24 v led driver ? nxp b.v. 2008. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com date of release: 15 january 2008 document identifier: pca9625_2 please be aware that important notices concerning this document and the product(s) described herein, have been included in section legal information. 23. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 ordering information . . . . . . . . . . . . . . . . . . . . . 3 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 functional description . . . . . . . . . . . . . . . . . . . 6 7.1 device addresses . . . . . . . . . . . . . . . . . . . . . . . 6 7.1.1 regular i 2 c-bus slave address . . . . . . . . . . . . . 6 7.1.2 led all call i 2 c-bus address . . . . . . . . . . . . . . 7 7.1.3 led sub call i 2 c-bus addresses . . . . . . . . . . . 7 7.1.4 software reset i 2 c-bus address . . . . . . . . . . . 7 7.2 control register . . . . . . . . . . . . . . . . . . . . . . . . . 8 7.3 register de?nitions . . . . . . . . . . . . . . . . . . . . . . 9 7.3.1 mode register 1, mode1 . . . . . . . . . . . . . . . . 10 7.3.2 mode register 2, mode2 . . . . . . . . . . . . . . . . 11 7.3.3 pwm0 to pwm15, individual brightness control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7.3.4 grppwm, group duty cycle control . . . . . . . . 12 7.3.5 grpfreq, group frequency . . . . . . . . . . . . . 12 7.3.6 ledout0 to ledout3, led driver output state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.3.7 subadr1 to subadr3, i 2 c-bus subaddress 1 to 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.3.8 allcalladr, led all call i 2 c-bus address. 14 7.4 active low output enable input . . . . . . . . . . . 14 7.5 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 15 7.6 software reset . . . . . . . . . . . . . . . . . . . . . . . . 15 7.7 individual brightness control with group dimming/blinking . . . . . . . . . . . . . . . . . . . . . . . 16 8 characteristics of the i 2 c-bus. . . . . . . . . . . . . 17 8.1 bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8.1.1 start and stop conditions . . . . . . . . . . . . . 17 8.2 system con?guration . . . . . . . . . . . . . . . . . . . 17 8.3 acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 18 9 bus transactions . . . . . . . . . . . . . . . . . . . . . . . 19 10 application design-in information . . . . . . . . . 21 11 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 22 12 thermal characteristics. . . . . . . . . . . . . . . . . . 22 13 static characteristics. . . . . . . . . . . . . . . . . . . . 23 14 dynamic characteristics . . . . . . . . . . . . . . . . . 24 15 test information . . . . . . . . . . . . . . . . . . . . . . . . 26 16 package outline . . . . . . . . . . . . . . . . . . . . . . . . 27 17 handling information . . . . . . . . . . . . . . . . . . . 28 18 soldering of smd packages . . . . . . . . . . . . . . 28 18.1 introduction to soldering. . . . . . . . . . . . . . . . . 28 18.2 wave and re?ow soldering . . . . . . . . . . . . . . . 28 18.3 wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 28 18.4 re?ow soldering. . . . . . . . . . . . . . . . . . . . . . . 29 19 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 30 20 revision history . . . . . . . . . . . . . . . . . . . . . . . 31 21 legal information . . . . . . . . . . . . . . . . . . . . . . 32 21.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 32 21.2 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 21.3 disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 32 21.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 32 22 contact information . . . . . . . . . . . . . . . . . . . . 32 23 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

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